In the course of System-On-Chip (SOC) application, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component or line that can be created using a fabrication process) has decreased. This scaling-down process generally provides benefits by increasing production efficiency and lowering associated costs. At the same time, the scaling-down process also increases the significance of process-induced inconsistency and environment-induced inconsistency of the components, between their actual sizes of critical dimensions (CDs) as manufactured in a real SOC product and those as designed in an Electronic Design Automation (EAD) tool.
With the development of portable electronic devices (such as smartphones or tablet personal computer), the multi-core SOC products are in a greater demand than the single-core SOC product. However, there are still challenges in reducing core-to-core mismatches in SOC products.
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale.